Digital System Design

Features

• This unique free application is for all students across the world. It covers 112 topics of Digital System Design in detail. These 112 topics are divided in 4 units.
• Each topic is around 600 words and is complete with diagrams, equations and other forms of graphical representations along with simple text explaining the concept in detail.
• This USP of this application is "ultra-portability". Students can access the content on-the-go from anywhere they like.
• Basically, each topic is like a detailed flash card and will make the lives of students simpler and easier.
• Some of topics Covered in this application are:
• 1. Multiple Processes
• 2. Architecture Body-Dataflow Style of Modeling
• 3. Introduction to VHDL.
• 4. VHDL Capabilities.
• 5. VHDL-Hardware Abstraction.
• 6. VHDL-Design Units
• 7. VHDL-Entity Declaration.
• 8. Architecture Body-Structural Style of Modeling
• 9. Architecture Body- Behavioral Style of Modeling
• 10. Architecture Body- Mixed Style of Modeling
• 11. Configuration Declaration
• 12. Package Declaration
• 13. Package Body
• 14. Model Analysis
• 15. VHDL-Basic Language Elements- Identifiers
• 16. VHDL-Basic Language Elements-Data Objects
• 17. VHDL-Data Types
• 18. Data Types-Scalar Types
• 19. Data Types-Scalar Types-Enumeration Types
• 20. Data Types-Scalar Types-Integer Types
• 21. Data Types-Scalar Types-Floating Point Types
• 22. Composite Type-Array Types
• 23. Record Types
• 24. Record Types
• 25. Access Types
• 26. Incomplete Types
• 27. File Types
• 28. Operators
• 29. Behavioral Modeling-Entity Declaration
• 30. Behavioral Modeling-Architecture Body
• 31. Behavioral Modeling-Process Statement
• 32. Behavioral Modeling-Variable Assignment Statement
• 33. Behavioral Modeling-Signal Assignment Statement
• 34. Behavioral Modeling-Wait Statement
• 35. Behavioral Modeling-Case Statement
• 36. Behavioral Modeling-If Statement
• 37. Behavioral Modeling-Null Statement and Loop Statement
• 38. Behavioral Modeling- Next Statement and Exit Statement
• 39. Behavioral Modeling-Assertion Statement
• 40. Behavioral Modeling- Inertial Delay Model and Transport Delay Model
• 41. Behavioral Modeling-Signal Drivers
• 42. Behavioral Modeling-Effect of Transport Delay on Signal Drivers
• 43. Effect of Inertial Delay on Signal Drivers
• 44. Dataflow Modeling-Concurrent Signal Assignment Statement
• 45. Dataflow Modeling-Delta Delay Revisited
• 46. Dataflow Modeling- Conditional Signal Assignment Statement
• 47. Dataflow Modeling-Selected Signal Assignment Statement
• 48. Dataflow Modeling-Concurrent Assertion Statement
• 49. Dataflow Modeling-Block Statement
• 50. Structural Modeling-Component Declaration
• 51. Structural Modeling-Component Instantiation
• 52. Structural Modeling- Resolving Signal Values
• 53. Packages-Package Declaration
• 54. Packages-Package Body
• 55. Design Libraries
• 56. Design File
• 57. Implicit and Explicit Visibility
• 58. Explicit Visibility-Library Clause and Use Clause
• 59. Subprograms
• 60. Functions
• 61. Procedures
• 62. Subprogram declaration
• 63. Subprogram Overloading
• 64. Operator Overloading
• 65. Generics
• 66. Generics-value Specification
• 67. Configuration Specification
• 68. Configuration Declaration
• 69. Entities and architectures.
• 70. Identifiers, spaces and comments.
• 71. Combinational building blocks-Three-state buffers
• 72. Combinational building blocks-Three-state buffers
• 73. Combinational building blocks-Standard logic package
• 74. Decoders-2 to 4 decoder
• 75. Seven-segment display
• 76. n to 2n decoder - shift operators
• 77. Multiplexers-4 to 1 multiplexer
• 78. Priority encoder
• 79. Priority encoder- Sequential VHDL
• 80. Adders-Functional model
• 81. Ripple adder-Functional model
• 82. Parity checker
• 83. Attributes
• 84. Synchronous sequential systems
• 85. Design of a three-bit counter
• 86. SR latch
• 87. D latch
• 88. Edge-triggered D flip-flop
• 89. Asynchronous set and reset
• 90. Synchronous set and reset and clock enable
• 91. JK and T flip-flops
• 92. Multiple bit register
• 93. Shift registers-Serial in parallel out

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